TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 275

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

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The DMA transfer procedure is as follows when in the Chain DMA mode.
Count Register Setting
Sets “0” to the PDMAC Count Register (PMDCTR).
DMA Command Descriptor Chain Construction
Constructs the DMA Command Descriptor Chain in memory.
PDMAC Status Register (PDMSTATUS) Clearing
Clears any remaining status from a previous DMA transfer.
PDMAC Configuration Register (PDMCFG) Setting
Clears the Channel Regster bit (CHRST) and makes settings such as the data transfer
direction (XFRDIRC) and the data transfer unit size (XFRSIZE).
DMA Transfer Initiation
Setting the address of the DMA Command descriptor that is at the beginning of the Chain
List in the PDMAC Chain Address Register (PDMCA) automatically initiates DMA
transfer.
First, the values stored in each field of the DMA Command Descriptor that is at the beginning
of the Chain List are read to each corresponding PDMAC Register, then DMA transfer is
performed according to the read values.
If a value other than “0” is stored in the PDMAC Chain Address Register (PDMCA), data
transfer of the size stored in the PDMAC Count Register is complete, then the DMA
Command Descriptor value for the memory address specified by the PDMAC Chain Address
Register is read.
When the Chain Address field value reads a descriptor of “0”, the PDMAC Chain Address
Register value is not updated and the previous value (address of the Data Command
Descriptor at which the Chain Address field value is “0” when read) is held.
0 value judgement is performed when the lower 32 bits of the PDMAC Chain Address
Register are rewritten. DMA transfer is automatically initiated if the value was not “0”.
Therefore, please write to the upper 32 bits first when writing to the PDMAC Chain Address
Register using a 32-bit Store instruction.
Termination Report
When DMA data transfer of all descriptor chains terminates normally, the Normal Chain
Complete bit (NCCMP) of the PDMAC Status Register is set. An interrupt is reported if the
Chain Termination Interrupt Enable bit (MCCMPIE) of the PDMAC Configuration register
(PDMCFG) is set.
Also, the Normal Data Transfer Complete bit (NTCMP) of the DPMAC Status Register is set
each time the DMA data transfer specified by a DMA Command Descriptor terminates
normally. An interrupt is reported if the Normal Data Transfer Complete Interrupt Enable bit
(NTCMPIE) of the PDMAC Configuration Register (PDMCFG) is set.
If an error is detected during DMA transfer, the error cause is recorded in the lower 5 bits of
the PDMAC Status Register and the transfer is aborted. An interrupt is then reported if the
Error Detection Interrupt Enable bit (ERRIE) of the PDMAC Configuration register is set.
10-17
Chapter 10 PCI Controller