TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 61

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Signal Name
Signal Name
ACRESET*
SYNC
SDOUT
SDIN[1]
SDIN[0]
BITCLK
NMI*
INT[5:0]
3.1.9
3.1.10
AC-link Interface Signals
Interrupt Signals
Output
Output
Output
Type
Type
Input
Input
Input
Input
Input
PU
PU
AC '97 Master H/W Reset
ACRESET* shares the pin with the DMAREQ[2] signal. The boot configuration signal on
the ADDR[9] pin selects between ACRESET* and DMAREQ[2] (refer to Section “3.3 Pin
multiplex”).
48 kHz Fixed Rate Sample Sync
SYNC shares the pin with the DMAACK[2] signal. The boot configuration signal on the
ADDR[9] pin selects between SYNC and DMAACK[2] (refer to Section “3.3 Pin
multiplex”).
Serial, Time Division Multiplexed, AC '97 Output Stream
SDOUT shares the pin with the PIO[4] signal. The boot configuration signal on the
ADDR[9] pin selects between SDOUT and PIO[4] (refer to Section “3.3 Pin multiplex”).
Serial, Time Division Multiplexed, AC ‘97 Input Stream
When this pin is used as SDIN[1], pull down by the resister on the board. (Regarding the
value of register, please ask the Engineering Department in Toshiba).
Serial, Time Division Multiplexed, AC '97 Input Stream
SDIN[0] shares the pin with the PIO[3] signal. The boot configuration signal on the
ADDR[9] pin selects between SDIN[0] and PIO[3] (refer to Section “3.3 Pin multiplex”).
When this pin is used as SDIN[0], pull down by the resister on the board. (Regarding the
value of register, please ask the Engineering Department in Toshiba).
12.288 MHz Serial Data Clock
BITCLK shares the pin with the PIO[2] signal. The boot configuration signal on the
ADDR[9] pin selects between BITCLK and PIO[2] (refer to Section “3.3 Pin multiplex”).
When this pin is used as BITCLK, pull down by the resister on the board. (Regarding the
value of register, please ask the Engineering Department in Toshiba).
Non-Maskable Interrupt
Non-maskable interrupt signal.
External Interrupt Requests
External interrupt request signals.
INT[4:3] share pins with other function signals (refer to Section “3.3 Pin multiplex”).
Table 3.1.9 AC-link Interface Signals
Table 3.1.10 Interrupt Signals
3-7
Description
Description
Chapter 3 Signals
Initial State
Initial State
Selected by
ADDR[9]
L: Low
H: Input
Selected by
ADDR[9]
L: Low
H: High
Selected by
ADDR[9]
L: Low
H: Input
Input
Input
Input
Input
Input