TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 111
TMPR4937XBG-300
Manufacturer Part Number
TMPR4937XBG-300
Description
Manufacturer
Toshiba
Datasheet
1.TMPR4937XBG-300.pdf
(552 pages)
Specifications of TMPR4937XBG-300
Family Name
TX49
Device Core Size
64b
Frequency (max)
300MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
BGA
Lead Free Status / Rohs Status
Compliant
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ACK*/READY
ADDR [19:0]
DATA [31:0]
SYSCLK
(Input)
OE*
CE*
7.3.6.3
Ready Mode
Ready input from an external device. Ready input is internally synchronized. See Section “7.3.7.5
Ready Input Timing” for more information regarding the operation timing.
performed to see whether the Ready signal was asserted. Since EBCCRn.WT[0] is used to indicate
the ACK*/ Ready Static/Dynamic mode, it is not used for setting the Wait cycle count. Therefore,
the Wait cycle count that can be set by the Ready mode is 0, 2, 4, 6, …, 62.
signal. When the number of wait cycle is other than zero, after waiting only for the specified
number of cycles, Ready check is started.
When in this mode, the ACK*/Ready pin becomes Ready input, and the cycle is ended by
When the Wait cycle count specified by EBCCREBCCRn.PWT:WT elapses, a check is
When the number of wait cycles is 0, Ready check is started in 1 cycle after asserting the CE*
The Ready mode does not support Burst access by the internal bus.
EBCCRn.PWT:WT=2
Start Ready Check
Figure 7.3.3 Ready Mode
7-11
Chapter 7 External Bus Controller
EBCCRn.SHWT=0
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