TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 373

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

R/WUB TWUB UODE
31:16
12:7
R/W
Bit
6:5
31
15
14
13
15
4
3
0
11.4.1
Mnemonic
R/W
14
1
RWUB
TWUB
UODE
UPEN
UEPS
SCS
R/W
Line Control Register 0 (SILCR0)
Line Control Register 1 (SILCR1)
13
0
These registers specify the format of asynchronous transmission/reception data.
Reserved
Receive Wake
Up Bit
Transmit Wake
Up Bit
Open Drain
Enable
Reserved
Clock Select
Even Parity
Select
Parity Check
Enable
Field Name
12
Figure 11.4.1 Line Control Register (1/2)
Reserved
Wake Up Bit for Receive (Default: 0)
When in the Multi-Controller System mode, this field selects whether to
receive address (ID) frames whose Wake Up bits (WUB) are “1” or to
receive data frames whose Wake Up bits (WUB) are “0”. This value is
undefined when not in the Multi-Controller System mode.
0: Receive data frames.
1: Receive address (ID) frames.
Wake Up Bit for Transmit (Default: 1)
When in the Multi-Controller System mode, this field specifies the Wake Up
bit (WUB). This value is undefined when not in the Multi-Controller System
mode.
0: Data frame transfer (WUB = 0)
1: Address (ID) frame transfer (WUB = 1)
TXD Open Drain Enable (Default: 0)
This field selects the output mode of the TXD signal. When in the Multi-
Controller System mode, the Slave Controller must set the TXD signal to
Open Drain.
0: Totem pole output
1: Open drain output
SIO Clock Select (Default: 00)
This field selects the serial transfer clock. The clock frequency that is the
serial transfer clock divided by 16 becomes the baud rate (bps).
00: Internal clock (IMBUSCLK)
01: Baud rate generator output that divided IMBUSCLK
10: External clock (SCLK)
11: Baud rate generator output that divided SCLK
UART Even Parity Select (Default: 0)
This field selects the parity mode.
0: Odd parity
1: Even parity
UART Parity Enable (Default: 0)
This field selects whether to perform the parity check. This bit must be
cleared in multidrop systems (i.e., when the UMODE field is 10 or 11.)
0: Disable the parity check
1: Enable the parity check
Reserved
11-13
7
0xF300 (Ch. 0)
0xF400 (Ch. 1)
6
Description
SCS
R/W
10
5
Chapter 11 Serial I/O Port
UEPS UPEN USBL
R/W
4
0
R/W
3
0
R/W
2
0
1
UMODE
R/W
00
Read/Write
16
R/W
R/W
R/W
R/W
R/W
R/W
0
⎯
⎯
: Type
: Initial value
: Type
: Initial value