TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 191
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TMPR4937XBG-300
Manufacturer Part Number
TMPR4937XBG-300
Description
Manufacturer
Toshiba
Datasheet
1.TMPR4937XBG-300.pdf
(552 pages)
Specifications of TMPR4937XBG-300
Family Name
TX49
Device Core Size
64b
Frequency (max)
300MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
BGA
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
TMPR4937XBG-300
Manufacturer:
TOSHIBA
Quantity:
16 845
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Part Number:
TMPR4937XBG-300
Manufacturer:
DSP
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63:36
35:3
Bit
2:0
8.4.6
63
47
31
15
Mnemonic
CHADDR
DMA Chain Address Register (DM0CHARn, DM1CHARn)
Offset Address: DMAC0 0xB000 (ch. 0) / 0xB040 (ch. 1) / 0xB080 (ch. 2) / 0xB0C0 (ch. 3)
Reserved
Chain Address
Reserved
Field Name
DMAC1 0xB800 (ch. 0) / 0xB840 (ch. 1) / 0xB880 (ch. 2) / 0xB8C0 (ch. 3)
Figure 8.4.6 DMA Chain Address Register
Chain Address (Default: undefined)
When Chain DMA transfer is executed, this register sets the physical
address of the next DMA Command Descriptor to be read. If DMA transfer
according to the current Channel Register setting ends and the Chain
Enable bit (DMCCRn.CHNEN) is set, then the DMA Command Descriptor
is loaded in the Channel Register starting from the address indicated by
this register.
When a value other than “0” is set in this register, the Chain Enable bit
(DMCCRn.CHNEN) and the Transfer Active bit (DMCCRn.XFACT) are set.
When “0” is set in this register, only the Chain Enable bit
(DMCCRn.CHNEN) is cleared.
When the Chain Address field value reads a DMA Command Descriptor of
0, the value of this register is not updated and the value before that one
(address of the Data Command Descriptor when the value of the Chain
Address field being read was “0”) is held.
Reserved
CHADDR[15:3]
R/W
⎯
CHADDR[31:16]
Reserved
8-35
R/W
⎯
Description
Chapter 8 DMA Controller
36
35
3
CHADDR[35:32]
2
R/W
⎯
Reserved
R/W
Read/Write
R/W
R/W
48
32
16
0
⎯
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
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