NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 99

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5.1.19
5.1.20
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e. prefetchable) from the CPU perspective.
PMBASEU1—Prefetchable Memory Base Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register in conjunction with the corresponding Upper Base Address register
controls the CPU to PCI Express link prefetchable memory access routing based on the
following formula:
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1 MB boundary.
PMLIMITU1—Prefetchable Memory Limit Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register in conjunction with the corresponding Upper Limit Address register
controls the CPU to PCI Express link prefetchable memory access routing based on the
following formula:
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1 MB aligned memory block.
The upper 12 bits of this register are read/write and correspond to address bits
The upper 12 bits of this register are read/write and correspond to address bits
31:4
15:4
3:0
Bit
3:0
Bit
PREFETCHABLE_MEMORY_BASE ≤ Address ≤ PREFETCHABLE_MEMORY_LIMIT
PREFETCHABLE_MEMORY_BASE ≤ Address ≤ PREFETCHABLE_MEMORY_LIMIT
Access
Access &
R/W
Default
000 h
R/W
0 h
RO
Reserved
Prefetchable Memory Base Address (MBASEU): Corresponds to A[35:32] of the
lower limit of the prefetchable memory range that will be passed to PCI Express link.
Prefetchable Memory Address Limit (PMLIMIT)
Corresponds to A[31:20] of the upper limit of the address range passed to PCI
Express link.
64-bit Address Support
Indicates the bridge 32-bit address support only
1
28-2Bh
0000000Fh
R/W;
32 bits
1
2C-2Fh
00000000h
R/W;
32 bits
Description
Description
99