NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 54

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

54
All other bits not decoded are read only 0. The PCI Express Base Address cannot be
less than the maximum address written to the Top of physical memory register
(TOLUD). Software must ensure that these ranges do not overlap with known ranges
located above TOLUD.
31:28
25:3
2:1
Bit
27
26
0
Access &
Default
R/W
R/W
R/W
R/W
R/W
E h
0b
0b
0h
PCI Express Base Address:
This field corresponds to bits 31 to 28 of the base address for PCI Express
enhanced configuration space. BIOS will program this register resulting in a base
address for a contiguous memory address space; size is defined by bits 2:1 of this
register.
This base address shall be assigned on a boundary consistent with the number of
buses (defined by the Length field in this register) above TOLUD and still within
total 36-bit addressable memory space. The address bits decoded depend on the
length of the region defined by this register.
The address used to access the PCI Express configuration space for a specific
device can be determined as follows:
PCI Express Base Address + Bus Number * 1 MB + Device Number * 32 KB +
Function Number * 4 KB
The address used to access the PCI Express configuration space for Device 1 or 3
in this component would be PCI Express Base Address + 0 * 1 MB + 1 * 32 KB +
0 * 4 KB = PCI Express Base Address + 32 KB. Remember that this address is the
beginning of the 4 KB space that contains both the PCI compatible configuration
space and the PCI Express extended configuration space.
128 MB Base Address Mask (128ADMSK): This bit is either part of the PCI
Express Base Address (R/W) or part of the Address Mask (RO, read 0b),
depending on the value of bits 2:1 in this register.
64 MB Base Address Mask (64ADMSK): This bit is either part of the PCI
Express Base Address (R/W) or part of the Address Mask (RO, read 0b),
depending on the value of bits 2:1 in this register
Reserved
Length (LENGTH): This Field describes the length of this region
Enhanced Configuration Space Region/Buses Decoded
PCIEXBAR Enable (PCIEXBAREN):
00: 256 MB (Buses 0-255). Bits 31:28 are decoded in the PCI Express Base
01:128 MB (Buses 0-127). Bits 31:27 are decoded in the PCI Express Base
10:64 MB (Buses 0-63). Bits 31:26 are decoded in the PCI Express Base
11:Reserved
0: The PCIEXBAR register is disabled. Memory read and write transactions
1: The PCIEXBAR register is enabled. Memory read and write transactions
Address Field
Address Field.
Address Field.
proceed as if there were no PCIEXBAR register. PCIEXBAR bits 31:26 are
R/W with no functionality behind them.
whose address bits 31:26 match PCIEXBAR will be translated to
configuration reads and writes within the MCH.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description