NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 70

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.1.38
4.1.39
4.1.40
70
SKPD—Scratchpad Data (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register holds 32 writable bits with no functionality. It is for the convenience of
BIOS.
CAPID0—Capability Identifier (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
EDEAP—Extended DRAM Error Address Pointer (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
71:28
27:24
23:16
31:0
15:8
7:0
7:1
Bit
Bit
Bit
0
00000000 h
Access &
Access &
Access &
Default
Default
RO 09h
RO 00h
RO 09h
Default
RO 1h
RO/S
R/W
0 b
Reserved
CAPID Version: This field has the value 0001b to identify the first revision of the
CAPID register definition.
CAPID Length: This field has the value 09h to indicate the structure length
(9 bytes).
Next Capability Pointer: This field is hardwired to 00h indicating the end of the
capabilities linked list.
CAP_ID: This field has the value 1001b to identify the CAP_ID assigned by the PCI
SIG for vendor dependent capability pointers.
Reserved
Extended Error Address Pointer (EEAP): This bit provides bit 32 of the error
address after any remapping when an ECC error occurs. This bit is concatenated
with bits 31:7 of the DEAP register to get bits 32:7 of the address in which an error
occurred. This bit is reset on PWROK.
Scratchpad Data: 1 DWord of data storage.
0
DC-DFh
00000000h
R/W
32 bits
0
E0-E8h
000000000001090009h
RO
72 bits
0
FCh
00h
RO/S
8 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description
Description
Description