NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 49

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.1.4
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
PCISTS—PCI Status (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This status register reports the occurrence of error events on Device 0’s PCI interface.
Since the MCH Device 0 does not physically reside on Primary PCI, many of the bits are
not implemented.
10:9
3:0
Bit
15
14
13
12
11
8
7
6
5
4
Access &
Default
R/WC
R/WC
R/WC
00 b
RO
0 b
0 b
0 b
0 b
RO
0 b
RO
RO
0 b
RO
1 b
RO
0 b
RO
1 b
Detected Parity Error (DPE):
Not implemented. Hardwired to 0.
Signaled System Error (SSE):
Software clears this bit by writing a 1 to it.
0: MCH Device 0 did Not generate a SERR message over DMI
1: MCH Device 0 generated a SERR message over DMI for any enabled Device 0
error condition. Device 0 error conditions are enabled in the PCICMD, and ERRCMD
registers. Device 0 error flags are read/reset from the PCISTS, or ERRSTS registers.
Received Master Abort Status (RMAS):
Software clears this bit by writing a 1 to it.
1: MCH generated a DMI request that received an Unsupported Request completion
packet.
Received Target Abort Status (RTAS):
Software clears this bit by writing a 1 to it.
1: MCH generated a DMI request that receives a Completer Abort completion
packet.
Signaled Target Abort Status (STAS):
Not implemented. Hardwired to 0. The MCH will not generate a Target Abort DMI
completion packet or Special Cycle.
DEVSEL Timing (DEVT):
Hardwired to "00". Device 0 does not physically connect to Primary PCI. These bits
are set to "00" (fast decode) so that optimum DEVSEL timing for Primary PCI is not
limited by the MCH.
Master Data Parity Error Detected (DPD):
Not implemented. Hardwired to 0.
Fast Back-to-Back (FB2B):
Hardwired to 1. Device 0 does not physically connect to the Primary PCI. This bit is
set to 1 (indicating fast back-to-back capability) so that the optimum setting for
Primary PCI is not limited by the MCH.
Reserved
66 MHz Capable:
Hardwired to 0. This bit does not apply to PCI Express.
Capability List (CLIST):
This bit is hardwired to 1 to indicate to the configuration software that this device/
function implements a list of new capabilities. A list of new capabilities is accessed
via the CAPPTR register (offset 34h). The CAPPTR register contains an offset
pointing to the start address within configuration space of this device where the
Capability standard register resides.
Reserved
0
06-07h
0090h
RO, R/WC
16 bits
Description
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