NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 153

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

System Address Map
8.3.2
8.3.3
8.3.4
8.4
8.4.1
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
HSEG (FEDA_0000h-FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window
to SMM space. It is sometimes called the High SMM memory space. SMM-mode CPU
accesses to the optionally enabled HSEG are remapped to 000A_0000h - 000B_FFFFh.
Non-SMM-mode CPU accesses to enabled HSEG are considered invalid and are
terminated immediately on the FSB. The exceptions to this rule are Non-SMM-mode
Write Back cycles which are remapped to SMM space to maintain cache coherency. PCI
Express and DMI originated cycles to enabled SMM space are not allowed. Physical
DRAM behind the HSEG transaction address is not remapped and is not accessible. All
Cacheline writes with WB attribute or Implicit write backs to the HSEG range are
completed to DRAM like an SMM cycle.
FSB Interrupt Memory Space (FEE0_0000-FEEF_FFFF)
The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any
device on PCI Express or DMI may issue a Memory Write to 0FEEx_xxxxh. The MCH will
forward this Memory Write along with the data to the FSB as an Interrupt Message
Transaction. The MCH terminates the FSB transaction by providing the response and
asserting HTRDY#. This Memory Write cycle does not go to DRAM.
High BIOS Area
The top 2 MB (FFE0_0000h -FFFF_FFFFh) of the PCI Memory Address Range is reserved
for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the
system BIOS. The CPU begins execution from the High BIOS after reset. This region is
mapped to the DMI so that the upper subset of this region aliases to the 16 MB–256 KB
range. The actual address space required for the BIOS is less than 2 MB, but the
minimum CPU MTRR range for this region is 2 MB so that full 2 MB must be considered.
Main Memory Address Space (4 GB to Remaplimit)
The maximum main memory size supported is 8 GB total DRAM memory. A hole
between TOLUD and 4 G occurs when main memory size approaches 4 GB or larger. As
a result, a TOM register and Remapbase/Remaplimit registers become relevant.
The new remap configuration registers exist to reclaim lost main memory space.
Upstream write accesses above 36-bit addressing will be treated as peer writes by PCI
Express and DMI. Upstream read accesses above 36-bit addressing will be treated as
invalid cycles by PCI Express and DMI.
Top of Memory
This “Top of Memory” register reflects the total amount of populated physical memory.
This is also the amount of addressable physical memory when remapping is used
appropriately to ensure that no physical memory is wasted. This is NOT necessarily the
highest main memory address (holes may exist in main memory address map due to
addresses allocated for memory mapped I/O).
TOLUD register is restricted to 4 GB memory (A[31:27]), but the MCH can support up
to 8 GB, limited by DRAM pins. For physical memory greater than 4 GB, the TOM
register helps identify the address range in between the 4 GB boundary and the top of
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