NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 92

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.4
92
PCISTS1—PCI Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register reports the occurrence of error conditions associated with primary side of
the “virtual” Host-PCI Express bridge embedded within the MCH.
10:9
2:0
Bit
15
14
13
12
11
8
7
6
5
4
3
Access &
Default
R/WC
00 b
RO
0 b
0 b
RO
0 b
RO
0 b
RO
0 b
RO
RO
0 b
RO
0 b
RO
0 b
RO
1 b
RO
0 b
Detected Parity Error (DPE)
Not Applicable or Implemented. Hardwired to 0. Parity (generating poisoned TLPs)
is not supported on the primary side of this device (The MCH does not do error
forwarding).
Signaled System Error (SSE)
This bit is set when this Device sends an SERR due to detecting an ERR_FATAL or
ERR_NONFATAL condition and the SERR Enable bit in the Command register is ‘1’.
Both received (if enabled by BCTRL1[1]) and internally detected error messages do
not affect this field.
Received Master Abort Status (RMAS)
Not Applicable or Implemented. Hardwired to 0. The concept of a master abort does
not exist on primary side of this device.
Received Target Abort Status (RTAS)
Not Applicable or Implemented. Hardwired to 0. The concept of a target abort does
not exist on primary side of this device.
Signaled Target Abort Status (STAS)
Not Applicable or Implemented. Hardwired to 0. The concept of a target abort does
not exist on primary side of this device.
DEVSELB Timing (DEVT)
This device is not the subtractive decoded device on bus 0. This bit field is therefore
hardwired to 00 to indicate that the device uses the fastest possible decode.
Master Data Parity Error (PMDPE)
Because the primary side of the PCI Express lane’s virtual PCI-to-PCI bridge is
integrated with the MCH functionality there is no scenario where this bit will get set.
Because hardware will never set this bit, it is impossible for software to have an
opportunity to clear this bit or otherwise test that it is implemented. The PCI
specification defines it as a R/WC, but for our implementation an RO definition
behaves the same way and will meet all Microsoft testing requirements.
Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hardwired to 0.
Reserved
66/60 MHz capability (CAP66)
Not Applicable or Implemented. Hardwired to 0.
Capabilities List
Indicates that a capabilities list is present. Hardwired to 1.
INTA Status
Indicates that an interrupt message is pending internally to the device. Only PME
and Hot Plug sources feed into this status bit (not PCI INTA-INTD assert and de-
assert messages). The INTA Assertion Disable bit, PCICMD1[10], has no effect on
this bit.
Reserved
1
06h
0010h
RO, R/WC
16 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Host-PCI Express Bridge Registers (D1:F0)