NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 97

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5.1.15
5.1.16
Note:
Note:
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
MBASE1—Memory Base Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express link non-prefetchable memory access
routing based on the following formula:
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A [31:20] of the 32-bit address. The bottom 4 bits of this register are
read-only and return zeroes when read. The configuration software must initialize this
register. For the purpose of address decode address bits A[19:0] are assumed to be 0.
Thus, the bottom of the defined memory address range will be aligned to a 1 MB
boundary.
MLIMIT1—Memory Limit Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express link non-prefetchable memory access
routing based on the following formula:
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A [31:20] of the 32-bit address. The bottom 4 bits of this register are
read-only and return zeroes when read. The configuration software must initialize this
register. For the purpose of address decode address bits A[19:0] are assumed to be
FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1 MB
aligned memory block.
Memory range covered by MBASE and MLIMIT registers are used to map non-pre-
fetchable PCI Express link address ranges and PMBASE and PMLIMIT are used to map
pre-fetchable address ranges.
This segregation allows application of USWC space attribute to be performed in a true
plug-and-play manner to the pre-fetchable address range for improved CPU-PCI
Express memory access performance.
Also that configuration software is responsible for programming all address range
registers (pre-fetchable, non-prefetchable) with the values that provide exclusive
address ranges i.e. prevent overlap with each other and/or with the ranges covered
with the main memory. There is no provision in the MCH hardware to enforce
prevention of overlap and operations of the system in the case of overlap are not
guaranteed.
15:4
3:0
Bit
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
Access &
Default
FFF h
R/W
Memory Address Base (MBASE)
Corresponds to A[31:20] of the lower limit of the memory range that will be passed
to PCI Express link.
Reserved
1
20h
FFF0h
R/W
16 bits
1
22h
0000h
R/W
16 bits
Description
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