NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 108

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.36
Note:
5.1.37
108
DCTL—Device Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
DSTS—Device Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Reflects status corresponding to controls in the Device Control register.
15:8
7:5
Bit
4
3
2
1
0
Access &
Default
000 b
R/W
R/W
R/W
R/W
R/W
0 b
0 b
0 b
0 b
Reserved
Max Payload Size
000:128B maximum supported payload for Transaction Layer Packets (TLP). As a
001-111: Reserved.
Reserved
Unsupported Request Reporting Enable
When set Unsupported Requests will be reported.
Note that reporting of error messages received by Root Port is controlled
exclusively by Root Control register.
Fatal Error Reporting Enable
When set fatal errors will be reported. For a Root Port, the reporting of fatal errors
is internal to the root. No external ERR_FATAL message is generated.
Non-Fatal Error Reporting Enable
When set non-fatal errors will be reported. For a Root Port, the reporting of non-
fatal errors is internal to the root. No external ERR_NONFATAL message is
generated. Uncorrectable errors can result in degraded performance.
Correctable Error Reporting Enable
When set correctable errors will be reported. For a Root Port, the reporting of
correctable errors is internal to the root. No external ERR_CORR message is
generated.
1
A8h
0000h
R/W
16 bits
1
AAh
0000h
RO
16 bits
receiver, the Device must handle TLPs as large as the set value; as
transmitter, the Device must not generate TLPs exceeding the set value.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host-PCI Express Bridge Registers (D1:F0)
Description