NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 117

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5.1.48
5.1.49
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
PVCCAP1—Port VC Capability Register 1 (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Describes the configuration of PCI Express Virtual Channels associated with this port.
PVCCAP2—Port VC Capability Register 2 (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Describes the configuration of PCI Express Virtual Channels associated with this port.
31:24
31:7
23:8
6:4
2:0
7:0
Bit
Bit
3
Access &
Access &
Default
Default
000 b
R/WO
001 b
00 h
01 h
RO
RO
RO
Reserved
Low Priority Extended VC Count
Indicates the number of (extended) Virtual Channels in addition to the default VC
belonging to the low-priority VC (LPVC) group that has the lowest priority with
respect to other VC resources in a strict-priority VC Arbitration.
The value of 0 in this field implies strict VC arbitration.
Reserved
Extended VC Count
Indicates the number of (extended) Virtual Channels in addition to the default VC
supported by the device.
BIOS Requirement: Set this field to 000b for all configurations. VC1 is not a POR
feature.
VC Arbitration Table Offset
Indicates the location of the VC Arbitration Table. This field contains the zero-based
offset of the table in DQWORDS (16 bytes) from the base address of the Virtual
Channel Capability Structure. A value of 0 indicates that the table is not present (due
to fixed VC priority).
Reserved
VC Arbitration Capability
Indicates that the only possible VC arbitration scheme is hardware fixed (in the root
complex).
VC1 is the highest priority, VC0 is the lowest priority.
1
104h
00000001h
RO, R/WO
32 bits
1
108h
00000001h
RO
32 bits
Description
Description
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