NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 82

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.3
Table 4-3.
Figure 4-1.
82
Egress Port Register Summary
Registers exist in the PCI Express Root Complex Link Declaration Capability structures
of each PCI Express element in both the MCH & ICH to support software discovery of
the topology of the root complex. They are offset from the EPBAR base address.
Table 4-3
order. Detailed bit descriptions of the registers follow the table. Link Declaration
Topology is shown in
Egress Port Register Address Map
Link Declaration Topology
044h–047h
050h–053h
058h–05Fh
060h–063h
068h–06Fh
070h–073h
078h–07Fh
x1, x4, x8, x16
Address
x1, x4, x8
Offset
provides an address map of the registers listed by address offset in ascending
Port #2
Port #3
PCIE0
PCIE1
Register
EPLE3D
EPLE3A
Symbol
EPLE1D
EPLE1A
EPLE2D
EPLE2A
EPESD
†
†
Figure
(Type 1)
EP Element Self Description
EP Link Entry 1 Description
EP Link Entry 1 Address
EP Link Entry 2 Description
EP Link Entry 2 Address
EP Link Entry 3 Description
EP Link Entry 3 Address
Link #4
4-1.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Register Name
Egress Port
Port #1
Port #0
DMI
x4
Host Bridge Registers (Device 0, Function 0)
0000000000000000h
0000000000008000h
0000000000018000h
See
Default Value
Egress Port
01000000h
02000002h
03000002h
Section 4.3.1
Port #0
MCH
ICH
R/WO, RO
R/WO, RO
R/WO, RO
R/WO, RO
Access
R/WO
RO
RO