NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 74

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.2.5
4.2.6
74
C0DRA0—Channel A DRAM Rank 0,1 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
The DRAM Rank Attribute Registers define the page sizes to be used when
accessing different ranks. These registers should be left with their default value (all
zeros) for any rank that is unpopulated, as determined by the corresponding CxDRB
registers. Each byte of information in the CxDRA registers describes the page size of a
pair of ranks.
Channel and rank map:
Channel A Rank 0, 1:108h
Channel A Rank 2, 3:109h
Channel B Rank 0, 1:188h
Channel B Rank 2, 3:189h
C0DRA2—Channel A DRAM Rank 2,3 Attribute
MMIO Range:
Address Offset:
Size:
The operation of this register is detailed in the description for register C0DRA0.
6:4
2:0
Bit
7
3
Access &
Default
000 b
000 b
R/W
R/W
Reserved
Channel A DRAM odd Rank Attribute: This 3 bit field defines the page size of the
corresponding rank.
Reserved
Channel A DRAM even Rank Attribute: This 3 bit field defines the page size of
the corresponding rank.
000:Unpopulated
001:Reserved
010:4 KB
011:8 KB
100:16 KB
Others:Reserved
000:Unpopulated
001:Reserved
010:4 KB
011:8 KB
100: 16 KB
Others:Reserved
MCHBAR
108h
00h
R/W
8 bits
MCHBAR
109h
8 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description