NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 84

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.3.3
4.3.4
84
EPLE1A—EP Link Entry 1 Address
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
This register provides the second part of a Link Entry, which declares an internal link to
another Root Complex Element.
EPLE2D—EP Link Entry 2 Description
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
This register provides the first part of a Link Entry, which declares an internal link to
another Root Complex Element.
63:32
31:12
31:24
23:16
15:2
11:0
Bit
Bit
Bit
1
0
Access &
Access &
Default
Default
Access &
0 0000 h
R/WO
R/WO
Default
02 h
00 h
RO
0 b
0 b
R/WO
RO
Reserved
Link Type
This field indicates that the link points to memory-mapped space (for RCRB). The
link address specifies the 64-bit base address of the target RCRB.
Link Valid
0: Link Entry is not valid and will be ignored.
1: Link Entry specifies a valid link.
Target Port Number
Specifies the port number associated with the element targeted by this link entry
(PCI Express). The target port number is with respect to the component that
contains this element as specified by the target component ID.
Target Component ID
Identifies the physical or logical component that is targeted by this link entry. A
value of 0 is reserved; Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
Reserved
Link Address
Memory mapped base address of the RCRB that is the target element (DMI) for
this link entry.
Reserved
EPBAR
058-05Fh
00000000_00000000h
R/WO
64 bits
EPBAR
060-063h
02000002h
RO, R/WO
32 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description
Description
Description