NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 125

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5.1.64
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
UEMSK—Uncorrectable Error Mask (D1:F0)
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Controls reporting of individual errors by the device (or logic associated with this port)
to the PCI Express Root Complex. As these errors are not originating on the other side
of a PCI Express link, no PCI Express error message is sent, but the unmasked error is
reported directly to the root control logic. A masked error (respective bit set to 1 in the
mask register) has no action taken. There is a mask bit per error bit of the
Uncorrectable Error Status register.
31:21
13:5
19:0
13:5
3:0
3:0
Bit
Bit
14
20
18
17
16
15
14
4
4
Access &
Access &
Default
Default
R/WC/S
R/WC/S
R/W/S
R/W/S
R/W/S
R/W/S
R/W/S
R/W/S
0 b
0 b
0 b
0 b
0 b
0 b
0 b
0 b
Completion Timeout Status
Reserved
Data Link Protocol Error Status (DLPES):
The Data Link Layer Protocol Error that causes this bit to be set will also cause the
Fatal Error Detected bit in Device Status[2] to be set if not already set.
Reserved
Reserved
Unsupported Request Error Mask
0 = Not Masked
1 = Masked
Reserved
Malformed TLP Mask
0 = Not Masked
1 = Masked
Receiver Overflow Mask
0 = Not Masked
1 = Masked
Unexpected Completion Mask
0 = Not Masked
1 = Masked
Reserved
Completion Timeout Mask
0 = Not Masked
1 = Masked
Reserved
Data Link Protocol Error Mask
0 = Not Masked
1 = Masked
Reserved
0/1/0/MMR
1C8-1CBh
00000000h
RO; R/W/S
32 bits
Description
Description
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