NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 42

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

3.4.2.2
3.5
42
DMI Configuration Accesses
Accesses to disabled MCH internal devices, bus numbers not claimed by the Host-PCI
Express bridge, or PCI Bus #0 devices not part of the MCH (#2 through #31) will be
subtractively decoded to the ICH7 and consequently be forwarded over the DMI via a
PCI Express configuration TLP.
If the Bus Number is zero, the MCH will generate a Type 0 Configuration Cycle TLP on
DMI. If the Bus Number is non-zero, and falls outside the range claimed by the Host-
PCI Express bridge, the MCH will generate a Type 1 Configuration Cycle TLP on DMI.
The ICH7 routes configurations accesses in a manner similar to the MCH. The ICH7
decodes the configuration TLP and generates a corresponding configuration access.
Accesses targeting a device on PCI Bus #0 may be claimed by an internal device. The
ICH7 compares the non-zero Bus Number with the Secondary Bus Number and
Subordinate Bus Number registers of its PCI-to-PCI bridges to determine if the
configuration access is meant for Primary PCI, one of the ICH7’s devices, the DMI, or
some other downstream PCI bus or PCI Express link.
Configuration accesses that are forwarded to the ICH7, but remain unclaimed by any
device or bridge will result in a master abort.
I/O Mapped Registers
The MCH contains two registers that reside in the CPU I/O address space: the
Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible
through the Configuration Data window.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
MCH Register Description