NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 64

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.1.30
4.1.31
64
TOLUD—Top of Low Usable DRAM (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This 8-bit register defines the Top of Low Usable DRAM. TSEG Memory are within the
DRAM space defined. From the top, MCH optionally claims 1, 2, or 8 MB of DRAM for
TSEG if enabled.
SMRAM—System Management RAM Control (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
The SMRAMC register controls how accesses to Compatible and Extended SMRAM
spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit
is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.
7:3
2:0
Bit
Bit
7
6
5
Access &
Default
R/W
01 h
Access &
Default
R/W/L
R/W/L
0 b
0 b
Top of Low Usable DRAM (TOLUD): This register contains bits 31 to 27 of an
address one byte above the maximum DRAM memory that is usable by the operating
system. Address bits 31 down to 27 programmed to 01h implies a minimum memory
size of 128 MBs.
Configuration software must set this value to the smaller of the following 2 choices:
Maximum amount memory in the system plus one byte or the minimum address
allocated for PCI memory.
Address bits 26:0 are assumed to be 000_0000 h for the purposes of address
comparison. The Host interface positively decodes an address towards DRAM if the
incoming address is less than the value programmed in this register.
If this register is set to 0000 0 b it implies 128 MBs of system memory.
Note: The Top of Low Usable DRAM is the lowest address above TSEG.
Reserved
Reserved
SMM Space Open (D_OPEN): (When D_OPEN=1 and D_LCK=0, the SMM space
DRAM is made visible even when SMM decode is not active. This is intended to help
BIOS initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1
are not set at the same time.
SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DRAM is not
accessible to data references, even if SMM decode is active. Code references may
still access SMM space DRAM. This will allow SMM software to reference through
SMM space to update the display even when SMM is mapped over the VGA range.
Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same
time. Note that the D_CLS bit only applies to Compatible SMM space.
0
9Ch
08h
R/W
8 bits
0
9Dh
02h
R/W, RO
8 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Host Bridge Registers (Device 0, Function 0)
Description