NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 154

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

8.4.2
8.4.3
8.4.4
154
physical memory. This identifies memory that can be directly accessed (no remap
address calculation) which is useful for memory access indication, early path indication,
and trusted read indication.
C1DRB3 cannot be used directly to determine the effective size of memory as the
values programmed in the DRB’s depend on the memory mode (stacked, interleaved).
The Remap Base/Limit registers also can not be used because remapping can be
disabled. The TOM register is used for early memory channel identification (channel A
vs. channel B) in the case of stacked memory.
Memory Re-claim Background
The following are examples of Memory Mapped IO devices which are typically located
below 4 GB:
In previous generation MCHs, the physical DRAM memory overlapped by the logical
address space allocated to these Memory Mapped I/O devices was unusable. The
result is that a large amount of physical memory populated in the system is unusable.
The MCH provides the capability to re-claim the physical memory overlapped by the
Memory Mapped I/O logical address space. The MCH re-maps physical memory from
the Top of Low Memory (TOLUD) boundary up to the 4 GB boundary to an equivalent
sized logical address range located just above the top of physical memory.
Memory Re-mapping
An incoming address (referred to as a logical address) is checked to see if it falls in the
memory re-map window. The bottom of the re-map window is defined by the value in
the REMAPBASE register. The top of the re-map window is defined by the value in the
REMAPLIMIT register. An address that falls within this window is remapped to the
physical memory starting at the address defined by the TOLUD register.
PCI Express Configuration Address Space
There is a device 0 register, PCIEXBAR, that defines the base address for the 256 MB
block of addresses below the top of addressable memory (currently 4 GB) for the
configuration space associated with all devices and functions that are potentially a part
• High BIOS
• HSEG
• TSEG
• XAPIC
• IO APIC
• Local APIC
• FSB Interrupts
• PCI Express BAR
• MCHBAR
• EPBAR
• DMIBAR
• PMBASE/PMLIMIT, including PMBASEU/PMLIMITU
• MBASE/MLIMIT
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
System Address Map