NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 165

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Functional Description
9.3
9.3.1
9.3.1.1
9.3.1.2
9.3.1.3
9.3.2
Note:
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
PCI Express
See
further details.
This MCH is part of a PCI Express root complex. This means it connects a host CPU/
memory subsystem to a PCI Express hierarchy. The control registers for this
functionality are located in device #1 (and device #3) configuration space and two Root
Complex Register Blocks (RCRBs). The DMI RCRB contains registers for control of the
ICH7 attach ports.
PCI Express Architecture
The PCI Express architecture is specified in layers. Compatibility with the PCI
addressing model (a load-store architecture with a flat address space) is maintained to
ensure that all existing applications and drivers operate unchanged. The PCI Express
configuration uses standard mechanisms as defined in the PCI Plug-and-Play
specification. The initial speed of 1.25 GHz (250 MHz internally) results in 2.5 Gb/s/
direction which provides a 250 MB/s communications channel in each direction
(500 MB/s total), which is close to twice the data rate of classic PCI per lane.
Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer’s primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also manages
flow control of TLPs.
Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and error
correction.
Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry.
Configurations (Intel® 3010 chipset only)
Section 9.3.2
These PCI Express ports will be referred to as the PCIE0 and PCIE1. Device 1 contains
the control registers for PCIE0. Device 3 contains the control registers for PCIE1.
The PCI Express links are mapped through separate PCI-PCI bridge structures.
Section 1
through
for a list of PCI Express features and the PCI Express specification for
Section 9.3.8
are for Intel® 3010 chipset only.
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