NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 51

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.1.8
4.1.9
4.1.10
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
HDR—Header Type (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register identifies the header layout of the configuration space. No physical
register exists at this location.
SVID—Subsystem Vendor Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register is used to identify the vendor of the subsystem.
SID—Subsystem Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register is used to identify a particular subsystem.
15:0
15:0
7:0
Bit
Bit
Bit
Access &
Access &
Access &
Default
Default
Default
0000 h
0000 h
R/WO
R/WO
00 h
RO
PCI Header (HDR):
This field always returns 0 to indicate that the MCH is a single function device with
standard header layout. Reads and writes to this location have no effect.
Subsystem Vendor ID (SUBVID):
This field should be programmed during boot-up to indicate the vendor of the
system board. After it has been written once, it becomes read only.
Subsystem ID (SUBID):
This field should be programmed during BIOS initialization. After it has been written
once, it becomes read only.
0
0Eh
00h
RO
8 bits
0
2C-2Dh
0000h
R/WO
16 bits
0
2E-2Fh
0000h
R/WO
16 bits
Description
Description
Description
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