NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 39

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

MCH Register Description
3.4
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
As with PCI devices, each device is selected based on decoded address information that
is provided as a part of the address portion of Configuration Request packets. A PCI
Express device will decode all address information fields (bus, device, function, and
extended address numbers) to provide access to the correct register.
To access this space (steps 1, 2 and 3 are done only once by BIOS),
Routing Configuration Accesses
The MCH supports two PCI related interfaces: DMI and PCI Express. The MCH is
responsible for routing PCI and PCI Express configuration cycles to the appropriate
device that is an integrated part of the MCH or to one of these two interfaces.
Configuration cycles to the ICH7 internal devices and Primary PCI (including
downstream devices) are routed to the ICH7 via DMI. Configuration cycles to both the
PCI compatibility configuration space and the PCI Express extended configuration space
are routed to the PCI Express port device or associated link.
1. Use the PCI compatible configuration mechanism to enable the PCI Express
2. Use the PCI compatible configuration mechanism to write an appropriate PCI
3. Calculate the host address of the register you wish to set using (PCI Express base
4. Use a memory write or memory read cycle to the calculated host address to write
enhanced configuration mechanism by writing 1 to bit 0 of the PCIEXBAR register.
Express base address into the PCIEXBAR register.
+ (bus number * 1 MB) + (device number * 32 KB) + (function number * 4 KB) +
(1 B * offset within the function) = host address).
or read that register.
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