NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 24

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

24
HD[63:0]#
HDSTBP[3:0]#
HDSTBN[3:0]#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HREQ[4:0]#
HTRDY#
HRS[2:0]#
BSEL[2:0]
Signal Name
CMOS
Type
GTL+
GTL+
GTL+
GTL+
GTL+
GTL+
GTL+
GTL+
GTL+
I/O
I/O
I/O
I/O
I/O
I/O
2x
2x
O
O
I
I
Host Data: These signals are connected to the CPU data bus. Data on
HD[63:0]# is transferred at 4x rate. Note that the data signals may be
inverted on the CPU bus, depending on the HDINV[3:0]# signals.
Differential Host Data Strobes: The differential source synchronous strobes
used to transfer HD[63:0]# and HDINV[3:0]# at 4x transfer rate.
These signals are named this way because they are not level sensitive. Data is
captured on the falling edge of both strobes. Hence, they are pseudo-
differential, and not true differential.
Hit: This signal indicates that a caching agent holds an unmodified version of
the requested line. It is also driven in conjunction with HHITM# by the target
to extend the snoop window.
Hit Modified: This signal indicates that a caching agent holds a modified
version of the requested line and that this agent assumes responsibility for
providing the line. This signal is also driven in conjunction with HHIT# to
extend the snoop window.
Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and
HADS#, until the negation of HLOCK# must be atomic (i.e. no DMI or PCI
Express accesses to DRAM are allowed when HLOCK# is asserted by the CPU).
Precharge Request: The CPU provides a “hint” to the MCH that it is OK to
close the DRAM page of the memory read request with which the hint is
associated. The MCH uses this information to schedule the read request to
memory using the special “AutoPrecharge” attribute. This causes the DRAM to
immediately close (Precharge) the page after the read data has been
returned. This allows subsequent CPU requests to more quickly access
information on other DRAM pages, since it will no longer be necessary to close
an open page prior to opening the proper page. HPCREQ# is asserted by the
requesting agent during both halves of Request Phase. The same information
is provided in both halves of the request phase.
Host Request Command: This signal defines the attributes of the request.
HREQ[4:0]# are transferred at 2x rate. They are asserted by the requesting
agent during both halves of Request Phase. In the first half the signals define
the transaction type to a level of detail that is sufficient to begin a snoop
request. In the second half the signals carry additional information to define
the complete transaction type.
Host Target Ready: This signal indicates that the target of the CPU
transaction is able to enter the data transfer phase.
Response
Signals: These
signals
indicates type
of response:
Bus Speed Select: At the de-assertion of RSTIN#, the value sampled on
these pins determines the expected frequency of the bus.
HDSTBP[3]#, HDSTBN[3]#
HDSTBP[2]#, HDSTBN[2]#
HDSTBP[1]#, HDSTBN[1]#
HDSTBP[0]#, HDSTBN[0]#
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Strobes
000
001
010
011
100
101
110
111
Encoding
Idle state
Retry response
Deferred response
Reserved (not driven by MCH)
Hard Failure (not driven by MCH)
No data response
Implicit Writeback
Normal data response
Description
HD[63:48]#
HD[47:32]#
HD[31:16]#
HD[15:0]#
Data
Response type
Signal Description
HDINV[3]#
HDINV[2]#
HDINV[1]#
HDINV[0]#
Bits