NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 116

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.46
5.1.47
116
PCI_EXPRESS_LC—PCI Express link Legacy Control
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Controls functionality that is needed by Legacy (non-PCI Express aware) Operating
Systems during run time.
VCECH—Virtual Channel Enhanced Capability Header
(D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Indicates PCI Express device Virtual Channel capabilities.
Note that extended capability structures for PCI Express devices are located in PCI
Express extended configuration space and have different field definitions than standard
PCI capability structures.
31:20
19:16
31:3
15:0
Bit
Bit
2
1
0
Access &
Access &
Default
Default
0002 h
140 h
R/W
R/W
R/W
RO
RO
1 h
RO
0 b
0 b
0 b
Pointer to Next Capability
The Link Declaration Capability is the next in the PCI Express extended capabilities
list.
PCI Express Virtual Channel Capability Version
Hardwired to 1 to indicate compliances with the 1.0a version of the PCI Express
specification.
Extended Capability ID
Value of 0002 h identifies this linked list item (capability structure) as being for PCI
Express Virtual Channel registers.
Reserved
PME GPE Enable (PMEGPE)
0: Do not generate GPE PME message when PME is received.
1: Generate a GPE PME message when PME is received (Assert_PMEGPE and
Hot-Plug GPE Enable (HPGPE)
0: Do not generate GPE Hot-Plug message when Hot-Plug event is received.
1: Generate a GPE Hot-Plug message when Hot-Plug Event is received
General Message GPE Enable (GENGPE)
0: Do not forward received GPE assert/deassert messages.
1: Forward received GPE assert/deassert messages. These general GPE message
Deassert_PMEGPE messages on DMI). This enables the MCH to support PMEs on
the PCI Express link port under legacy OSs.
(Assert_HPGPE and Deassert_HPGPE messages on DMI). This enables the MCH
to support Hot-Plug on the PCI Express link port under legacy OSs.
can be received via the PCI Express link port from an external Intel device (i.e.
Intel® 6702PXH 64-bit PCI Hub) and will be subsequently forwarded to the ICH7
(via Assert_GPE and Deassert_GPE messages on DMI). For example, an
Intel® 6702PXH 64-bit PCI Hub might send this message if a PCI Express device
is hot plugged into an Intel® 6702PXH 64-bit PCI Hub port.
1
ECh
00000000h
RO, R/W
32 bits
1
100h
14010002h
RO
32 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Host-PCI Express Bridge Registers (D1:F0)