NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 4

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4
4.2
4.3
4.1.14 PCIEXBAR—PCI Express Register Range Base Address (D0:F0) .....................53
4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) .....................55
4.1.16 DEVEN—Device Enable (D0:F0) ................................................................56
4.1.17 DEAP - DRAM Error Address Pointer (D0:F0)...............................................56
4.1.18 DERRSYN - DRAM Error Syndrome (D0:F0) ................................................57
4.1.19 DERRDST - DRAM Error Destination (D0:F0)...............................................57
4.1.20 PAM0—Programmable Attribute Map 0 (D0:F0) ...........................................58
4.1.21 PAM1—Programmable Attribute Map 1 (D0:F0) ...........................................59
4.1.22 PAM2—Programmable Attribute Map 2 (D0:F0) ...........................................59
4.1.23 PAM3—Programmable Attribute Map 3 (D0:F0) ...........................................60
4.1.24 PAM4—Programmable Attribute Map 4 (D0:F0) ...........................................60
4.1.25 PAM5—Programmable Attribute Map 5 (D0:F0) ...........................................61
4.1.26 PAM6—Programmable Attribute Map 6 (D0:F0) ...........................................61
4.1.27 LAC—Legacy Access Control (D0:F0) .........................................................62
4.1.28 REMAPBASE - Remap Base Address Register ..............................................63
4.1.29 REMAPLIMIT - Remap Limit Address Register..............................................63
4.1.30 TOLUD—Top of Low Usable DRAM (D0:F0) .................................................64
4.1.31 SMRAM—System Management RAM Control (D0:F0)....................................64
4.1.32 ESMRAMC—Extended System Management RAM Control (D0:F0) ..................65
4.1.33 TOM - Top of Memory..............................................................................66
4.1.34 ERRSTS—Error Status (D0:F0) .................................................................67
4.1.35 ERRCMD—Error Command (D0:F0) ...........................................................68
4.1.36 SMICMD - SMI Command (D0:F0).............................................................69
4.1.37 SCICMD - SCI Command (D0:F0) .............................................................69
4.1.38 SKPD—Scratchpad Data (D0:F0)...............................................................70
4.1.39 CAPID0—Capability Identifier (D0:F0) .......................................................70
4.1.40 EDEAP—Extended DRAM Error Address Pointer (D0:F0) ...............................70
MCHBAR Configuration Register Details.................................................................71
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10 C0DRC0—Channel A DRAM Controller Mode 0 .............................................77
4.2.11 C0DRC1—Channel A DRAM Controller Mode 1 .............................................78
4.2.12 C1DRB0—Channel B DRAM Rank Boundary Address 0..................................79
4.2.13 C1DRB1—Channel B DRAM Rank Boundary Address 1..................................79
4.2.14 C1DRB2—Channel B DRAM Rank Boundary Address 2..................................79
4.2.15 C1DRB3—Channel B DRAM Rank Boundary Address 3..................................79
4.2.16 C1DRA0—Channel B DRAM Rank 0,1 Attribute ............................................79
4.2.17 C1DRA2—Channel B DRAM Rank 2,3 Attribute ............................................79
4.2.18 C1DCLKDIS—Channel B DRAM Clock Disable ..............................................80
4.2.19 C1BNKARC—Channel B Bank Architecture ..................................................80
4.2.20 C1DRT1—Channel 1 DRAM Timing Register 1 .............................................80
4.2.21 C1DRC0—Channel 1 DRAM Controller Mode 0 .............................................80
4.2.22 C1DRC1—Channel 1 DRAM Controller Mode 1 .............................................80
4.2.23 PMCFG—Power Management Configuration.................................................81
4.2.24 PMSTS—Power Management Status...........................................................81
Egress Port Register Summary ............................................................................82
4.3.1
4.3.2
4.3.3
C0DRB0—Channel A DRAM Rank Boundary Address 0..................................72
C0DRB1—Channel A DRAM Rank Boundary Address 1..................................73
C0DRB2—Channel A DRAM Rank Boundary Address 2..................................73
C0DRB3—Channel A DRAM Rank Boundary Address 3..................................73
C0DRA0—Channel A DRAM Rank 0,1 Attribute ............................................74
C0DRA2—Channel A DRAM Rank 2,3 Attribute ............................................74
C0DCLKDIS—Channel A DRAM Clock Disable ..............................................75
C0BNKARC—Channel A DRAM Bank Architecture .........................................76
C0DRT1—Channel A DRAM Timing Register ...............................................76
EPESD—EP Element Self Description..........................................................83
EPLE1D—EP Link Entry 1 Description .........................................................83
EPLE1A—EP Link Entry 1 Address..............................................................84
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet