NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 100

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.21
5.1.22
100
configuration software between the memory ranges that must be defined as UC and the
ones that can be designated as a USWC (i.e. prefetchable) from the CPU perspective.
CAPPTR1—Capabilities Pointer (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
The capabilities pointer provides the address offset to the location of the first entry in
this device’s linked list of capabilities.
INTRLINE1—Interrupt Line (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register contains interrupt line routing information. The device itself does not use
this value; rather device drivers and operating systems to determine priority and vector
information use it.
Note that prefetchable memory range is supported to allow segregation by the
7:0
31:4
3:0
Bit
7:0
Bit
Bit
R/W
00 h
Access
Access &
Access &
R/W
Default
Default
88h
RO
Reserved
Prefetchable Memory Address Limit (MLIMITU): Corresponds to A[35:32] of the
upper limit of the prefetchable Memory range that will be passed to PCI Express link.
First Capability (CAPPTR1)
The first capability in the list is the Subsystem ID and Subsystem Vendor ID
Capability.
Interrupt Connection. Used to communicate interrupt line routing information.
POST software writes the routing information into this register as it initializes and
configures the system. The value in this register indicates which input of the system
interrupt controller this device’s interrupt pin is connected to.
1
34h
88h
RO
8 bits
1
3Ch
00h
R/W
8 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Description
Host-PCI Express Bridge Registers (D1:F0)