NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 50

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.1.5
4.1.6
4.1.7
50
RID—Revision Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register contains the revision number of the MCH Device 0. These bits are read
only and writes to this register have no effect.
CC—Class Code (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register identifies the basic function of the device, a more specific sub-class, and a
register-specific programming interface.
MLT—Master Latency Timer (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Device 0 in the MCH is not a PCI master. Therefore, this register is not implemented.
23:16
15:8
7:0
7:0
7:0
Bit
Bit
Bit
Access &
Access &
Access &
Default
Default
Default
06 h
00 h
00 h
C0h
RO
RO
RO
RO
Revision Identification Number (RID):
This is an 8-bit value that indicates the revision identification number for the MCH
Device 0.
Base Class Code (BCC):
This is an 8-bit value that indicates the base class code for the MCH.
06h: Bridge device.
Sub-Class Code (SUBCC):
This is an 8-bit value that indicates the category of Bridge into which the MCH falls.
00h: Host Bridge.
Programming Interface (PI):
This is an 8-bit value that indicates the programming interface of this device. This
value does not specify a particular register set layout and provides no practical use
for this device.
Reserved
0
08h
C0h
RO
8 bits
0
09-0Bh
060000h
RO
24 bits
0
0Dh
00h
RO
8 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description
Description
Description