NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 25

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Signal Description
2.2
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
DDR2 DRAM Channel A Interface
PM_BMBUSY#
HRCOMP
HSCOMP
HSWING
HDVREF
HACCVREF
SCB_A[7:0]
SCLK_A[5:0]
SCLK_A[5:0]#
SCS_A[3:0]#
SMA_A[13:0]
SBS_A[2:0]
SRAS_A#
SCAS_A#
SWE_A#
SDQ_A[63:0]
SDM_A[7:0]
SDQS_A[8:0]
Signal Name
Signal Name
HVCMOS
CMOS
CMOS
Type
I/O
I/O
A
A
A
I
I
I
I
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
Type
I/O
I/O
I/O
2x
2x
2x
2x
O
O
O
O
O
O
O
O
O
Slew Rate Compensation Select:
1: Normal Operation - use Lookup table for slew compensation value.
0: Use SCOMP circuit for slew compensation value.
Host RCOMP: This signal is used to calibrate the Host GTL+ I/O buffers.
This signal is powered by the Host Interface termination rail (Vtt).
Slew Rate Compensation: This signal provides compensation for the Host
Interface.
Host Voltage Swing: This signal provides the reference voltage used by FSB
RCOMP circuits. HSWING is used for the signals handled by HRCOMP.
Host Reference Voltage: This signal is the reference voltage input for the
Data signals of the Host GTL interface.
Host Reference Voltage. This signal is the reference voltage input for the
Address and Common clock signals of the Host GTL interface.
ECC Check Byte: These signals are used for ECC.
SDRAM Differential Clock: (3 per DIMM) SCLK_A and its
complement SCLK_A# signal make a differential clock pair output.
The crossing of the positive edge of SCLK_A and the negative edge
of its complement SCLK_A# are used to sample the command and
control signals on the SDRAM.
SDRAM Complementary Differential Clock: (3 per DIMM)
These are the complementary differential DDR2 clock signals.
Chip Select: (1 per Rank) These signals select particular SDRAM
components during the active state. There is one Chip Select for
each SDRAM rank.
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM
Bank Select: These signals define which banks are selected
within each SDRAM rank. DDR2: 1 Gb technology is 8 banks.
Row Address Strobe: This signal is used with SCAS_A# and
SWE_A# (along with SCS_A#) to define the SDRAM commands.
Column Address Strobe: This signal is used with SRAS_A# and
SWE_A# (along with SCS_A#) to define the SDRAM commands.
Write Enable: This signal is used with SCAS_A# and SRAS_A#
(along with SCS_A#) to define the SDRAM commands.
Data Lines: SDQ_A signals interface to the SDRAM data bus.
Data Mask: When activated during writes, the corresponding data
groups in the SDRAM are masked. There is one SDM_A signal for
every data byte lane.
Data Strobes: For DDR2, SDQS_A and its complement SDQS_A#
signal make up a differential strobe pair. The data is captured at
the crossing point of SDQS_A and its complement SDQS_A#
during read and write transactions.
Description
Description
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