NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 147

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

System Address Map
8.1.1
8.1.2
8.1.3
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
DOS Range (0h – 9_FFFFh)
The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to
the main memory controlled by the MCH.
Legacy Area (A_0000h-B_FFFFh)
The legacy 128 KB VGA memory range, frame buffer, (000A_0000h – 000B_FFFFh) can
be mapped to PCI Express (Device #1 or 3), and/or to the DMI. The appropriate
mapping depends on which devices are enabled and the programming of the VGA
steering bits. Based on the VGA steering bits, priority for VGA mapping is constant. The
MCH always decodes internally mapped devices first. Internal to the MCH. The MCH
always positively decodes internally mapped devices, PCI Express. Subsequent
decoding of regions mapped to PCI Express or the DMI depends on the Legacy VGA
configuration bits (VGA Enable & MDAP); see LAC Register (Device 0, offset 97h). This
region is also the default for SMM space.
Compatible SMRAM Address Range (A_0000h-B_FFFFh)
When compatible SMM space is enabled, SMM-mode CPU accesses to this range are
routed to physical system DRAM at 000A 0000h - 000B FFFFh. Non-SMM-mode CPU
accesses to this range are considered to be to the Buffer Area as described above. PCI
Express and DMI originated cycles to enabled SMM space are not allowed and are
considered to be to the Buffer Area. PCI Express and DMI initiated cycles are attempted
as Peer cycles, and will master abort on PCI if no external VGA device claims them.
Monochrome Adapter (MDA) Range (B_0000h-B_7FFFh)
Legacy support requires the ability to have a second controller (monochrome) in the
system. Accesses in the standard VGA range are forwarded to PCI Express, or the DMI
(depending on configuration bits). Since the monochrome adapter may be mapped to
any one of these devices, the MCH must decode cycles in the MDA range (000B_0000h
- 000B_7FFFh) and forward either to PCI Express, or the DMI. This capability is
controlled by a VGA steering bits and the legacy configuration bit (MDAP bit). In
addition to the memory range B0000h to B7FFFh, the MCH decodes IO cycles at 3B4h,
3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards them to the either PCI Express, and/
or the DMI.
PCI Express 16-bit VGA Decode
In the PCI to PCI Bridge Architecture Specification Revision 1.2, it is required that 16-
bit VGA decode be a feature. The VGA 16-bit decode: originally was described in an
ECR to the PCI to PCI Bridge Architecture Specification Revision 1.1. This is now listed
as a required feature in the updated 1.2 specification.
Expansion Area (C_0000h-D_FFFFh)
This 128-KB ISA Expansion region (000C_0000h – 000D_FFFFh) is divided into eight
16-KB segments (see
states: read-only, write-only, read/write, or disabled. Typically, these blocks are
mapped through MCH and are subtractively decoded to ISA space. Memory that is
disabled is not remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
Table
8-1). Each segment can be assigned one of four Read/Write
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