NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 164

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Table 9-5.
Note:
9.2.2.4
9.2.3
9.2.4
164
256
x16
256
512
x16
512
x16
Mb
Mb
Mb
Mb
Gb
Gb
x8
x8
x8
1
1
4i
4i
4i
4i
8i
8i
KB
KB
KB
KB
KB
KB
4
8
8
8
4
8
128
256
256
512
512
MB
MB
MB
MB
MB
GB
1
DRAM Address Translation (Dual Channel Interleaved Mode)
b - ‘bank’ select bit
c - ‘column’ address bit
h - ‘channel’ select bit
r - ‘row’ address bit
ECC Support
The MCH supports ECC (Error Checking and Correction) and uses an ECC algorithm to
protect against soft errors, when enabled. The algorithm works on a QWord (64-bit)
basis. It will correct any single-bit error and detect any two-bit errors. An odd number
of errors greater than 1, will either be detected correctly or will be misinterpreted as a
single-bit error, and cannot be corrected. An error in an even number of bits greater
than two will either be detected as a multi-bit error or it may not be detected at all.
DRAM Clock Generation
The MCH generates three differential clock pairs for every supported DIMM. There are
total of 6 clock pairs driven directly by the MCH to two DIMMs per channel.
DDR2 On Die Terminations
On die termination (ODT) is a feature that allows a DRAM to turn on/off internal
termination resistance for each DQ, DM, DQS, and DQS# signal for x8 and x16
configurations via the ODT control signals. The ODT feature is designed to improve
signal integrity of the memory channel by allowing the termination resistance for the
DQ, DM, DQS, and DQS# signals to be located inside the DRAM devices themselves
instead of on the motherboard. The MCH drives out the required ODT signals, based on
memory configuration and which rank is being written to or read from, to the DRAM
devices on a targeted DIMM rank to enable or disable their termination resistance.
3
1
13
3
0
r
13
11
11
2
9
r
r
r
12
12
12
12
12
2
8
r
r
r
r
r
10
10
10
10
10
10
2
7
r
r
r
r
r
r
2
6
9
9
9
9
9
9
r
r
r
r
r
r
2
5
8
8
8
8
8
8
r
r
r
r
r
r
2
4
7
7
7
7
7
7
r
r
r
r
r
r
2
3
6
6
6
6
6
6
r
r
r
r
r
r
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
2
2
5
5
5
5
5
5
r
r
r
r
r
r
2
1
4
4
4
4
4
4
r
r
r
r
r
r
2
0
3
3
3
3
3
3
r
r
r
r
r
r
1
9
2
2
2
2
2
2
r
r
r
r
r
r
1
8
1
1
1
1
1
1
r
r
r
r
r
r
1
7
0
0
0
0
0
0
r
r
r
r
r
r
11
11
11
11
1
6
b
0
b
0
r
r
r
r
12
1
5
1
1
1
1
1
r
b
b
b
b
b
1
4
b
0
b
0
b
0
b
0
b
2
b
2
1
3
b
1
9
9
9
9
9
c
c
c
c
c
1
2
8
8
8
8
8
8
c
c
c
c
c
c
Functional Description
1
1
c
7
c
7
c
7
c
7
c
7
c
7
1
0
c
6
c
6
c
6
c
6
c
6
c
6
9
5
5
5
5
5
5
c
c
c
c
c
c
8
4
4
4
4
4
4
c
c
c
c
c
c
7
3
3
3
3
3
3
c
c
c
c
c
c
6
h
h
h
h
h
h
5
2
2
2
2
2
2
c
c
c
c
c
c
4
1
1
1
1
1
1
c
c
c
c
c
c
3
c
0
c
0
c
0
c
0
c
0
c
0