NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 111

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5.1.40
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
LSTS—Link Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Indicates PCI Express link status.
15:13
9:4
3:0
Bit
12
11
10
Access &
Default
00 h
1 b
0 b
0 b
1 h
RO
RO
RO
RO
RO
Reserved
Slot Clock Configuration
0:
1:
Link Training
Indicates that Link training is in progress. Hardware clears this bit once Link training
is complete.
Training Error
This bit is set by hardware upon detection of unsuccessful training of the Link to the
L0 Link state.
Negotiated Width
Indicates negotiated link width
00h:
01h:
04h:
08h:
10h:
All other encodings are reserved.
Negotiated Speed
Indicates negotiated link speed.
1h:
All other encodings are reserved.
1
B2h
1001h
RO
16 bits
The device uses an independent clock irrespective of the presence of a
The device uses the same physical reference clock that the platform provides
Reserved
x1
x4
x8
x16 (Intel® 3010 chipset only)
2.5 Gb/s
reference on the connector.
on the connector.
Reserved (Intel® 3000 chipset only)
Description
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