NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 143

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

System Address Map
8
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
System Address Map
The MCH supports 64 GB of addressable memory space and 64 KB+3 bytes of
addressable I/O space. A programmable memory address space under the 1 MB region
is divided into regions which can be individually controlled with programmable
attributes such as Disable, Read/Write, Write Only, or Read Only. This section focuses
on how the memory space is partitioned and what the separate memory regions are
used for. I/O address space has simpler mapping and is explained near the end of this
section.
Addressing of memory ranges larger than 4 GB is supported. The HREQ[4:3] FSB pins
are decoded to determine whether the access is above or below 4 GB.
The MCH does support PCI Express link port upper prefetchable base/limit registers.
This allows the PCI Express link to claim I/O accesses above 32 bit. Addressing of
greater than 4 GB is allowed on both the DMI Interface and PCI Express interface. The
MCH supports a maximum of 8 GB of DRAM, no DRAM memory will be accessible above
12 GB. DRAM capacity is limited by the number of address pins available. There is no
hardware lock to prevent the situation where more memory than is addressable is
inserted.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the DMI. The exception to this rule is VGA ranges, which may be mapped to
PCI Express, DMI. In the absence of more specific references, cycle descriptions
referencing PCI should be interpreted as the DMI/PCI, while cycle descriptions
referencing PCI Express are related to the PCI Express bus. The TOLUD register is set
to the appropriate value by BIOS. The remapbase/remaplimit registers remap logical
accesses bound for addresses above 4 G onto physical addresses that fall within DRAM.
The Address Map includes a number of programmable ranges:
1. Device 0:
D. DMIBAR – This window is used to access registers associated with the MCH/
A. EPBAR – Egress port registers. Necessary for setting up VC1 as an isochronous
B. MCHBAR – Memory mapped range for internal MCH registers. For example,
C. PCIEXBAR – Flat memory-mapped address space to access device configuration
E. IFPBAR - Any write to this window will trigger a flush of the MCH’s Global Write
channel using time based weighted round robin arbitration. (4 KB window)
memory buffer register controls. (16 KB window)
registers. This mechanism can be used to access PCI configuration space (0-
FFh) and Extended configuration space (100h-FFFh) for PCI Express devices.
This enhanced configuration access mechanism is defined in the PCI Express
specification. (64 MB, 128 MB, or 256 MB window)
ICH7 (DMI) register memory range. (4 KB window)
Buffer to let software guarantee coherency between writes from an isochronous
agent and writes from the CPU (4 KB window).
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