NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 139

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Direct Media Interface (DMI) RCRB
7.1.8
7.1.9
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
DMIVC1RCAP—DMI VC1 Resource Capability
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
DMIVC1RCTL1—DMI VC1 Resource Control
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
Controls the resources associated with Virtual Channel 1.
31:16
30:27
26:24
23:20
19:17
14:8
16:8
7:0
7:1
Bit
Bit
15
31
0
Access &
Access &
Default
Default
001 b
01 h
R/W
R/W
R/W
R/W
00 h
1 b
0 b
0 h
0 h
RO
RO
RO
Reserved
Reject Snoop Transactions (RTS)
All snoopable transactions on VC1 are rejected. This VC is for isochronous transfers
only.
Reserved
Port Arbitration Capability (PAC)
Indicates the port arbitration capability is time-based WRR of 128 phases.
Virtual Channel Enable (EN)
R/W. Enables the VC when set. Disables the VC when cleared.
Reserved
Virtual Channel Identifier (ID)
Indicates the ID to use for this virtual channel.
Reserved
Port Arbitration Select (PAS)
Indicates which port table is being programmed. The only permissible value of this
field is 4h for the time-based WRR entries.
Reserved
Transaction Class / Virtual Channel Map (TVM)
Indicates which transaction classes are mapped to this virtual channel. When a bit is
set, this transaction class is mapped to the virtual channel.
Reserved
DMIBAR
01Ch
00008001h
RO
32 bits
DMIBAR
020h
01000000h
RO, R/W
32 bits
Description
Description
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