NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 105

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5.1.30
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
The reporting of the existence of this capability can be disabled by setting MSICH (CAPL
[0] @ 7Fh). In that case walking this linked list will skip this capability and instead go
directly from the PCI PM capability to the PCI Express capability.
MC—Message Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
System software can modify bits in this register, but the device is prohibited from doing
so.
If the device writes the same message multiple times, only one of those messages is
guaranteed to be serviced. If all of them must be serviced, the device must not
generate the same message again until the driver services the earlier one.
15:8
15:8
7:0
6:4
3:1
Bit
Bit
7
0
Access &
Access &
Default
Default
000 b
000 b
A0 h
05 h
R/W
R/W
RO
RO
RO
0 b
RO
0 b
Pointer to Next Capability
This contains a pointer to the next item in the capabilities list which is the PCI
Express capability.
Capability ID
Value of 05h identifies this linked list item (capability structure) as being for MSI
registers.
Reserved
64-bit Address Capable
Hardwired to 0 to indicate that the function does not implement the upper 32 bits of
the Message Address register and is incapable of generating a 64-bit memory
address.
Multiple Message Enable (MME)
System software programs this field to indicate the actual number of messages
allocated to this device. This number will be equal to or less than the number
actually requested.
The encoding is the same as for the MMC field below.
Multiple Message Capable (MMC)
System software reads this field to determine the number of messages being
requested by this device.
Value: Number of Messages Requested
000:1
All other’s are reserved in this implementation:
001:Reserved
010:Reserved
011:Reserved
100:Reserved
101:Reserved
110:Reserved
111:Reserved
MSI Enable (MSIEN) Controls the ability of this device to generate MSIs.
0: MSI will not be generated.
1: MSI will be generated when we receive PME or HotPlug messages. INTA will not
be generated and INTA Status (PCISTS1[3]) will not be set.
1
92h
0000h
RO, R/W
16 bits
Description
Description
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