NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 158

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

8.5.9
8.5.10
8.5.11
158
The CPU allows 64 K+3 bytes to be addressed within the I/O space. The MCH
propagates the CPU I/O address without any translation on to the destination bus and
therefore provides addressability for 64 K+3 byte locations. Note that the upper 3
locations can be accessed only during I/O address wrap-around when CPU bus HA[16]#
address signal is asserted. HA[16]# is asserted on the CPU bus whenever an I/O access
is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. HA[16]# is also asserted
when an I/O access is made to 2 bytes from address 0FFFFh.
The I/O accesses (other than ones used for configuration space access) are forwarded
normally to the DMI bus unless they fall within the PCI Express I/O address range as
defined by the mechanisms explained below. I/O writes are not posted. Memory writes
to ICH7 or PCI Express are posted. The PCICMD1 register can disable the routing of I/O
cycles to PCI Express.
The MCH responds to I/O cycles initiated on PCI Express or DMI with a UR status.
Upstream I/O cycles and configuration cycles should never occur. If one does occur, the
request will route as a read to memory address 0h so a completion is naturally
generated (whether the original request was a read or write). The transaction will
complete with a UR completion status.
For Pentium® processors, I/O reads that lie within 8-byte boundaries but cross 4-byte
boundaries are issued from the CPU as 1 transaction. The MCH will break this into 2
separate transactions. I/O writes that lie within 8-byte boundaries but cross 4-byte
boundaries are assumed to be split into 2 transactions by the CPU.
PCI Express I/O Address Mapping
The MCH can be programmed to direct non-memory (I/O) accesses to the PCI Express
bus interface when CPU initiated I/O cycle addresses are within the PCI Express I/O
address range. This range is controlled via the I/O Base Address (IOBASE) and I/O
Limit Address (IOLIMIT) registers in MCH Device #1 configuration space.
MCH Decode Rules and Cross-Bridge Address Mapping
The following are MCH decode rules and cross-bridge address mapping used in this
chipset:
Legacy VGA and I/O Range Decode Rules
The legacy 128 KB VGA memory range 000A_0000h-000B_FFFFh can be mapped to
PCI Express (Device #1), and/or to the DMI depending on the programming of the VGA
steering bits. Priority for VGA mapping is constant in that the MCH always decodes
internally mapped devices first. The MCH always positively decodes internally mapped
devices, namely PCI Express. Subsequent decoding of regions mapped to PCI Express
or the DMI depends on the Legacy VGA configurations bits (VGA Enable & MDAP) in the
LAC register (Device 0).
• VGAA = 000A_0000 – 000A_FFFF
• MDA = 000B_0000 – 000B_7FFF
• VGAB = 000B_8000 – 000B_FFFF
• MAINMEM = 0100_0000 to TOLUD
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
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System Address Map