NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 78

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.2.11
78
C0DRC1—Channel A DRAM Controller Mode 1
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
30:0
6:4
3:2
1:0
Bit
Bit
31
Access &
Access &
Default
Default
000 b
R/W
R/W
0 b
RO
Enhanced Addressing Enable (ENHADE):
Intel Reserved
Mode Select (SMS): These bits select the special operational mode of the DRAM
interface. The special modes are intended for initialization at power up.
When the MCH exits reset (power-up or otherwise), the mode select field is cleared
to "000". During any reset sequence, while power is applied and reset is active,
the MCH de-asserts all CKE signals. After internal reset is de-asserted, CKE signals
remain de-asserted until this field is written to a value different than "000". On this
event, all CKE signals are asserted. During suspend, MCH internal signal triggers
DRAM controller to flush pending commands and enter all ranks into Self-Refresh
mode. As part of resume sequence, MCH will be reset, which will clear this bit field
to "000" and maintain CKE signals de-asserted. After internal reset is de-asserted,
CKE signals remain de-asserted until this field is written to a value different than
"000". On this event, all CKE signals are asserted. During entry to other low power
states (C3, S1), MCH internal signal triggers DRAM controller to flush pending
commands and enter all ranks into Self-Refresh mode. During exit to normal
mode, MCH signal triggers DRAM controller to exit Self-Refresh and resume normal
operation without S/W involvement.
Reserved
DRAM Type (DT)
Used to select between supported SDRAM types.
0: Disabled. DRAM address map follows the standard address map.
1: Enabled. DRAM address map follows the enhanced address map.
000:
001:
010:
011:
100:
110:
111:
00:Reserved
01:Reserved
10:Second Revision Dual Data Rate (DDR2) SDRAM
11:Reserved
MCHBAR
124-127h
00000000h
R/W
32 bits
Post Reset state:
NOP Command Enable:
All CPU cycles to DRAM result in a NOP command on the DRAM
interface.
All Banks Pre-charge Enable:
All CPU cycles to DRAM result in an "all banks precharge" command on
the DRAM interface.
Mode Register Set Enable:
All CPU cycles to DRAM result in a "mode register" set command on the
DRAM interface. Host address lines are mapped to DRAM address lines
in order to specify the command sent, as shown in Volume 1, System
Memory Controller section, memory Detection and Initialization. Refer to
JEDEC Standard 79-2A Section 2.2.2 "Programming the Mode and
Extended Mode Registers".
Extended Mode Register Set Enable:
All CPU cycles to DRAM result in an "extended mode register set"
command on the DRAM interface. Host address lines are mapped to
DRAM address lines in order to specify the command sent, as shown in
Volume 1, System Memory Controller section, memory Detection and
Initialization. Refer to JEDEC Standard 79-2A Section 2.2.2
"Programming the Mode and Extended Mode Registers".
CBR Refresh Enable:
In this mode all CPU cycles to DRAM result in a CBR cycle on the DRAM
interface
Normal operation
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description
Description