NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 129

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D3:F0) (Intel® 3010 Chipset only)
6
Warning:
Table 6-1.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host-PCI Express Bridge
Registers (D3:F0) (Intel®
3010 Chipset only)
This chapter is for the Intel® 3010 chipset only.
Device 3 contains the controls associated with the PCI Express root port. In addition, it
also functions as the virtual PCI-to-PCI bridge.
the D3:F0 registers listed by address offset in ascending order.
detailed bit description of the registers.
When reading the PCI Express “conceptual” registers such as this, you may not get a
valid value unless the register value is stable.
The PCI Express Specification defines two types of reserved bits: Reserved and
Preserved:
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are
part of the Reserved and Preserved type, which have historically been the typical
definition for Reserved.
It is important to note that most (if not all) control bits in this device cannot be
modified unless the link is down. Software is required to first Disable the link, then
program the registers, and then re-enable the link (which will cause a full-retrain with
the new settings).
Host-PCI Express Bridge Register Address Map (D3:F0) (Sheet 1 of 3)
1. Reserved for future RW implementations; software must preserve value read for
2. Reserved and Zero: Reserved for future R/WC/S implementations; software must
Address
00-01h
02-03h
04-05h
06-07h
09-0Bh
0F-17h
Offset
writes to bits.
use 0 for writes to bits.
0Dh
08h
0Ch
0Eh
18h
19h
1Ah
Register Symbol
SUBUSN3
PCICMD3
PCISTS3
PBUSN3
SBUSN3
HDR3
VID3
DID3
RID3
CC3
CL3
—
—
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Class Code
Cache Line Size
Reserved
Header Type
Reserved
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Register Name
Table 6-1
provides an address map of
Default Value
060400h
Section 6.1
8086h
277Ah
0000h
0010h
C0h
00h
01h
00h
00h
00h
—
—
provides a
RO, R/WC
RO, R/W
Access
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
—
—
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