NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 16

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

1.2
16
Reference Documents
Note:
Intel® ICH7
INTx
MCH
MSI
PCI Express
Primary PCI
SCI
SEC
SERR
SMI
Rank
TOLM
VCO
Intel® 3000 and 3010 Chipset Memory Controller
Hub (MCH) Thermal/Mechanical Design Guidelines
Advanced Configuration and Power Interface
Specification
PCI Express Specification
DDR2 JEDEC Component Spec
Term
For the latest revision and documentation number, please contact your appropriate field representative.
Document Name
Seventh generation I/O Controller Hub component that contains additional functionality
compared to previous Intel® ICHs, which contain the primary PCI interface, LPC
interface, USB2, ATA-100, and other I/O functions. It communicates with the MCH over a
proprietary interconnect called DMI. For this MCH, the term ICH refers to Intel®
ICH7
An interrupt request signal where X stands for interrupts A,B,C and D.
Memory Controller Hub component that contains the processor interface, DRAM
controller, and PCI Express port. It communicates with the I/O controller hub (Intel®
ICH7) over the DMI. Throughout this document, MCH refers to the Intel® 3000
MCH and Intel® 3010 MCH, unless otherwise specified.
Message Signaled Interrupt. A transaction initiated outside the host, conveying interrupt
information to the receiving agent through the same path that normally carries read and
write commands.
Third Generation Input Output called PCI Express. A high-speed serial interface whose
configuration is software compatible with the existing PCI specifications.
The physical PCI bus that is driven directly by the ICH7 component. Communication
between Primary PCI and the MCH occurs over DMI. Note that the Primary PCI bus is not
PCI Bus 0 from a configuration standpoint.
System Control Interrupt. Used in ACPI protocol.
Single-bit Error Correct
An indication that an unrecoverable error has occurred on an I/O bus.
System Management Interrupt. Used to indicate any of several system conditions such as
thermal sensor events, throttling activated, access to System Management RAM, chassis
open, or other system state related activity.
A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four x16 SDRAM
devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a
single side of a DIMM.
Top Of Low Memory. The highest address below 4 GB for which a processor-initiated
memory read or write transaction will create a corresponding cycle to DRAM on the
memory interface.
Voltage Controlled Oscillator
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Version
1.0a
3.0
Description
NOTE
http://www.acpi.info/
http://www.pcisig.com/specifications
NOTE
Availability
Introduction