NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 72

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.2.1
72
C0DRB0—Channel A DRAM Rank Boundary Address 0
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
The DRAM Rank Boundary Register defines the upper boundary address of each
DRAM rank with a granularity of 32 MB. Each rank has its own single-byte DRB register.
These registers are used to determine which chip select will be active for a given
address.
Channel and rank map:
Channel A Rank 0:
Channel A Rank 1:
Channel A Rank 2:
Channel A Rank 3:
Channel B Rank 0:
Channel B Rank 1:
Channel B Rank 2:
Channel B Rank 3:
Single Channel or Asymmetric Channels Example
Interleaved Channels Example
If the channels are independent, addresses in Channel B should begin where
addresses in Channel A left off, and the address of the first rank of Channel A can
be calculated from the technology (256 Mb, 512 Mb, or 1 Gb) and the x8 or x16
configuration. With independent channels a value of 01h in C0DRB0 indicates that
32 MB of DRAM has been populated in the first rank, and the top address in that
rank is 32 MB.
If channels are interleaved, corresponding ranks in opposing channels will contain
the same value, and the value programmed takes into account the fact that twice
as many addresses are spanned by this rank compared to the single channel case.
With interleaved channels, a value of 01h in C0DRB0 and a value of 01h in
C1DRB0 indicate that 32 MB of DRAM has been populated in the first rank of each
channel and the top address in that rank of either channel is 64 MB.
— Programming guide:
— Programming guide:
If Channel A is empty, all of the C0DRBs are programmed with 00h.
C0DRB0 = Total memory in chA rank0 (in 32 MB increments)
C0DRB1 = Total memory in chA rank0 + chA rank1 (in 32 MB increments)
––––
C1DRB0 = Total memory in chA rank0 + chA rank1 + chA rank2 + chA rank3 +
chB rank0 (in 32 MB increments)
If Channel B is empty, all of the C1DRBs are programmed with the same value
as C0DRB3.
C0DRB0 = C1DRB0 = Total memory in chA rank0 (in 32 MB increments)
C0DRB1 = C1DRB1 = Total memory in chA rank0 + chA rank1 (in 32 MB
increments)
––––
C0DRB3 = C1DRB3 = Total memory in chA rank0 + chA rank1+ chA rank2 +
chA rank3 (in 32 MB increments)
MCHBAR
100h
00h
R/W
8 bits
100h
101h
102h
103h
180h
181h
182h
183h
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)