NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 35

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

MCH Register Description
3.2
Note:
Note:
Figure 3-1.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Platform Configuration
In platforms that support DMI (such as this MCH) the configuration structure is
significantly different from previous hub architectures. The DMI physically connects the
MCH and the ICH7; so, from a configuration standpoint, the DMI is logically PCI bus 0.
As a result, all devices internal to the MCH and the ICH7 appear to be on PCI bus 0.
The ICH7 internal LAN controller does not appear on bus 0; it appears on the external
PCI bus and this number is configurable.
The system’s primary PCI expansion bus is physically attached to the ICH7 and, from a
configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI
bridge; therefore, it has a programmable PCI Bus number. The PCI Express link
appears to system software to be a real PCI bus behind a PCI-to-PCI bridge that is a
device resident on PCI bus 0.
A physical PCI bus 0 does not exist; DMI and the internal devices in the MCH and ICH7
logically constitute PCI Bus 0 to configuration software. This is shown in
Conceptual Platform PCI Configuration Diagram
NOTE 1: Device 3 is for Intel® 3010 chipset only.
The MCH contains two (three for Intel® 3010 chipset) PCI devices within a single
physical component. The configuration registers for the two devices are mapped as
devices residing on PCI bus 0.
• Device 0: Host Bridge/DRAM Controller. Logically this appears as a PCI device
• Device 1 and Device 3 (Device 3 is for Intel® 3010 chipset only): Host-PCI
residing on PCI bus 0. Device 0 contains the standard PCI header registers, PCI
Express base address register, DRAM control (including thermal/throttling control),
and configuration for the DMI and other MCH specific registers.
Express Bridge. Logically this appears as a “virtual” PCI-to-PCI bridge residing on
PCI bus 0 and is compatible with PCI Express Specification Rev 1.0a. Device 1 and
3 contains the standard PCI-to-PCI bridge registers and the standard PCI Express/
PCI configuration registers (including the PCI Express memory address mapping).
It also contains Isochronous and Virtual Channel controls in the PCI Express
extended configuration space.
Host-PCI Express* Bridge
Bus 0 Device 1
or Device 3
1
PCI Configuration in I/O
Direct Media Interface
Processor
DRAM Controller
Interface Device
Bus 0 Device 0
MCH
Section
3-1.
35