NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 101

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5.1.23
5.1.24
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
INTRPIN1—Interrupt Pin (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register specifies which interrupt pin this device uses.
BCTRL1—Bridge Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (i.e. PCI
Express link) as well as some bits that affect the overall behavior of the “virtual” Host-
PCI Express bridge embedded within MCH, e.g. VGA compatible address ranges
mapping.
7:0
15:12
Bit
Bit
11
10
9
8
7
6
5
4
RO
01 h
Access &
Access &
Default
Default
R/W
R/W
RO
0 b
RO
0 b
RO
0 b
RO
0 b
RO
0 b
0 b
RO
0 b
0 b
Reserved
Interrupt Pin. As a single function device, the PCI Express device specifies INTA as
its interrupt pin.
01h=INTA.
Discard Timer SERR Enable
Not Applicable or Implemented. Hardwired to 0.
Discard Timer Status
Not Applicable or Implemented. Hardwired to 0.
Secondary Discard Timer
Not Applicable or Implemented. Hardwired to 0.
Primary Discard Timer
Not Applicable or Implemented. Hardwired to 0.
Fast Back-to-Back Enable (FB2BEN)
Not Applicable or Implemented. Hardwired to 0.
Secondary Bus Reset (SRESET)
Setting this bit triggers a hot reset on the corresponding PCI Express Port.
Master Abort Mode (MAMODE)
When acting as a master, unclaimed reads that experience a master abort returns
all 1’s and any writes that experience a master abort completes normally and the
data is thrown away. Hardwired to 0.
VGA 16-bit Decode
Enables the PCI-to-PCI bridge to provide 16-bit decoding of VGA I/O address
precluding the decoding of alias addresses every 1 KB. This bit only has meaning if
bit 3 (VGA Enable) of this register is also set to 1, enabling VGA I/O decoding and
forwarding by the bridge.
0 : Execute 10-bit address decodes on VGA I/O accesses.
1 : Execute 16-bit address decodes on VGA I/O accesses.
1
3Dh
01h
RO
8 bits
1
3Eh
0000h
RO, R/W
16 bits
Description
Description
101