NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 172

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

9.3.8
9.4
9.5
172
PCI Express Interrupt and GPE Flow
Each PCI Express port individually sends a single Assert/Deassert message to DMI for
legacy interrupts, MSIs, and GPEs. The XT PCI and GPE interrupts need to be routed
and connected to the DMI block. The only PCI legacy interrupt sent by the new Device
3 from internally generated sources is INTA, just like all other MCH internal devices.
The Device 1 and Device 3 bridge devices can pass along INTA-INTD from the PCI
Express link to DMI.
Power Management
Power Management features include:
Clocking
The MCH has PLLs to providing the internal clocks. The PLLs are:
For system clock diagram, please refer to the latest Intel® 3000 and 3010 Chipset
Platform Design Guide.
• ACPI 1.0b support
• ACPI S0, S4, S5, C0, and C1 states
• Enhanced power management state transitions for increasing time CPU spends in
• PCI Express Link States: L0, L0s, L1, L2/L3 Ready, L3
• Host PLL – Generates the main core clocks in the host clock domain. This PLL can
• Memory PLL – Can be used to generate memory core clocks, when not generated
• PCI Express PLL – Generates all PCI Express related clocks, including the Direct
low power states
also be used to generate memory core clocks. It uses the Host clock (HCLK) as a
reference.
by the Host PLL. This PLL is not needed in all configurations, but exists to provide
more flexible frequency combinations without an unreasonable VCO frequency. It
uses the Host clock (HCLK) as a reference.
Media Interface that connects to the ICH7. This PLL uses the 100 MHz (GCLK) as a
reference.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
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Functional Description