NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 68

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.1.35
68
ERRCMD—Error Command (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register controls the MCH responses to various system errors. Since the MCH does
not have an SERRB signal, SERR messages are passed from the MCH to the ICH7 over
DMI. When a bit in this register is set, a SERR message will be generated on DMI
whenever the corresponding flag is set in the ERRSTS register. The actual generation of
the SERR message is globally enabled for Device 0 via the PCI Command register.
15:12
7:2
Bit
11
10
9
8
1
0
Access &
Default
R/W
R/W
R/W
R/W
R/W
0 b
0 b
0 b
0 b
0 b
Reserved
SERR on MCH Thermal Sensor Event (TSESERR)
Reserved
SERR on LOCK to non-DRAM Memory (LCKERR)
SERR on DRAM Refresh Timeout (DRTOERR)
Reserved
SERR Multiple-Bit DRAM ECC Error (DMERR):
SERR on Single-bit ECC Error (DSERR):
For systems that do not support ECC this bit must be disabled.
1: The MCH generates a DMI SERR special cycle when bit 11 of the ERRSTS is
0: Reporting of this condition via SERR messaging is disabled.
1: The MCH will generate a DMI SERR special cycle whenever a CPU lock cycle
0: Reporting of this condition via SERR messaging is disabled.
1: The MCH generates a DMI SERR special cycle when a DRAM Refresh timeout
0: Reporting of this condition via SERR messaging is disabled.
1: The MCH generates an SERR message over DMI when it detects a multiple-
0: Reporting of this condition via SERR messaging is disabled. For systems not
1: The MCH generates an SERR special cycle over DMI when the DRAM
0: Reporting of this condition via SERR messaging is disabled.
0
CA-CBh
0000h
R/W
16 bits
set. The SERR must not be enabled at the same time as the SMI for the
same thermal sensor event.
is detected that does not hit DRAM.
occurs.
bit error reported by the DRAM controller.
supporting ECC this bit must be disabled.
controller detects a single bit error.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description