NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 95

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5.1.11
5.1.12
5.1.13
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
SUBUSN1—Subordinate Bus Number (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express link. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express link.
IOBASE1—I/O Base Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express link I/O access routing based on the
following formula:
Only upper 4 bits are programmable. For the purpose of address decode address bits A
[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be
aligned to a 4 KB boundary.
IOLIMIT1—I/O Limit Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express link I/O access routing based on the
following formula:
7:0
7:4
3:0
Bit
Bit
IO_BASE ≤ address ≤ IO_LIMIT
IO_BASE ≤ address ≤ IO_LIMIT
Access &
Access &
Default
Default
00 h
R/W
R/W
F h
Subordinate Bus Number (BUSN)
This register is programmed by configuration software with the number of the
highest subordinate bus that lies behind the device 1 bridge. When only a single PCI
device resides on the PCI Express link segment, this register will contain the same
value as the SBUSN1 register.
I/O Address Base (IOBASE)
Corresponds to A [15:12] of the I/O addresses passed by bridge 1 to PCI Express
link. BIOS must not set this register to 00h otherwise 0CF8h/0CFCh accesses will be
forwarded to the PCI Express hierarchy associated with this device.
Reserved
1
1Ah
00h
R/W
8 bits
1
1Ch
F0h
RO
8 bits
1
1Dh
00h
R/W
8 bits
Description
Description
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