NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 60

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.1.23
4.1.24
60
PAM3—Programmable Attribute Map 3 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from
0D0000h-0D7FFFh.
PAM4—Programmable Attribute Map 4 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from
0D8000h-0DFFFFh.
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
Bit
Bit
Access &
Access &
Default
Default
00 b
00 b
00 b
00 b
R/W
R/W
R/W
R/W
Reserved
0D4000-0D7FFF Attribute (HIENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0D4000 to 0D7FFF.
Reserved
0D0000-0D3FFF Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0D0000 to 0D3FFF.
Reserved
0DC000-0DFFFF Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0DC000 to 0DFFFF.
Reserved
0D8000-0DBFFF Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0D8000 to 0DBFFF.
0
93h
00h
R/W
8 bits
0
94h
00h
R/W
8 bits
00:DRAM Disabled: Accesses are directed to the DMI.
01:Read Only: All reads are serviced by DRAM. All writes are forwarded to the
10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
00:DRAM Disabled: Accesses are directed to the DMI.
01:Read Only: All reads are serviced by DRAM. All writes are forwarded to the
10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
00:DRAM Disabled: Accesses are directed to the DMI.
01:Read Only: All reads are serviced by DRAM. All writes are forwarded to the
10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
00:DRAM Disabled: Accesses are directed to the DMI.
01:Read Only: All reads are serviced by DRAM. All writes are forwarded to the
10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
DMI.
DMI.
DMI.
DMI.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description
Description