NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 75

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.2.7
Note:
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
C0DCLKDIS—Channel A DRAM Clock Disable
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
This register can be used to disable the System Memory Clock signals to each DIMM
slot, which can significantly reduce EMI and Power concerns for clocks that go to
unpopulated DIMMs. Clocks should be enabled based on whether a slot is populated,
and what kind of DIMM is present.
Since there are multiple clock signals assigned to each Rank of a DIMM, it is important
to clarify exactly which Rank width field affects which clock signal:
7:6
Bit
5
4
3
2
1
0
Channel
0
0
1
1
Access &
Default
R/W
R/W
R/W
R/W
R/W
R/W
0 b
0 b
0 b
0 b
0 b
0 b
Reserved
DIMM clock gate enable pair 5
DIMM clock gate enable pair 4
DIMM clock gate enable pair 3
DIMM clock gate enable pair 2
DIMM clock gate enable pair 1
DIMM clock gate enable pair 0
0: Tri-state the corresponding clock pair.
1: Enable the corresponding clock pair.
0: Tri-state the corresponding clock pair.
1: Enable the corresponding clock pair.
0: Tri-state the corresponding clock pair.
1: Enable the corresponding clock pair.
0: Tri-state the corresponding clock pair.
1: Enable the corresponding clock pair.
0: Tri-state the corresponding clock pair.
1: Enable the corresponding clock pair.
0: Tri-state the corresponding clock pair.
1: Enable the corresponding clock pair.
MCHBAR
10Ch
00h
R/W
8 bits
0 or 1
2 or 3
0 or 1
2 or 3
Rank
SCLK_A[2:0]/ SCLK_A[2:0]#
SCLK_A[5:3]/ SCLK_A[5:3]#
SCLK_B[2:0]/ SCLK_B[2:0]#
SCLK_B[5:3]/ SCLK_B[5:3]#
Clocks Affected
Description
75