NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 106

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.31
5.1.32
5.1.33
106
MA—Message Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MD—Message Data (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
PCI_EXPRESS_CAPL—PCI Express Link Capability List
(D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Enumerates the PCI Express link capability structure.
31:2
15:0
15:8
1:0
7:0
Bit
Bit
Bit
00000000 h
Access &
Access &
Default
Access &
Default
Default
0000 h
00 h
10 h
R/W
RO
RO
00 b
R/W
RO
Pointer to Next Capability
This value terminates the capabilities list. The Virtual Channel capability and any
other PCI Express specific capabilities that are reported via this mechanism are in a
separate capabilities list located entirely within PCI Express Extended Configuration
space.
Capability ID
Identifies this linked list item (capability structure) as being for PCI Express
registers.
Message Data
Base message data pattern assigned by system software and used to handle an MSI
from the device.
When the device must generate an interrupt request, it writes a 32-bit value to the
memory address specified in the MA register. The upper 16 bits are always set to 0.
This register supplies the lower 16 bits.
Message Address
Used by system software to assign an MSI address to the device.
The device handles an MSI by writing the padded contents of the MD register to
this address.
Force DWord Align
Hardwired to 0 so that addresses assigned by system software are always aligned
on a Dword address boundary.
1
94h
00000000h
RO, R/W
32 bits
1
98h
0000h
R/W
16 bits
1
A0h
0010h
RO
16 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Host-PCI Express Bridge Registers (D1:F0)
Description