NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 134

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

6.1.4
6.1.5
134
ESD3—Element Self Description (D3:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Provides information about the root complex element containing this Link Declaration
Capability.
LE2A3—Link Entry 2 Address (D3:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Second part of a Link Entry, which declares an internal link to another Root Complex
Element.
31:24
23:16
63:20
19:15
15:8
14:0
7:4
3:0
Bit
Bit
Access &
Default
Access &
0 0001 b
R/WO
Default
02 h
00 h
02 h
RO
RO
RO
0 h
RO
Port Number
Specifies the port number associated with this element with respect to the
component that contains this element. The egress port of the component to provide
arbitration to this Root Complex Element utilizes this port number value.
Component ID
Identifies the physical component that contains this Root Complex Element.
Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
Number of Link Entries
Indicates the number of link entries following the Element Self Description. This field
reports 2 (to Egress port and peer PCI Express port).
Reserved
Element Type
Indicates the type of the Root Complex Element.
Value of 0 h represents a root port.
Reserved
Device Number
Target for this link is PCIE0 (Device 1)
Reserved
3
144h
03000200h
RO, R/WO
32 bits
3
168h
0000000000010000h
R/O
64 bits
Host-PCI Express Bridge Registers (D3:F0) (Intel® 3010 Chipset only)
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
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Description
Description